Santa Clara, California, April 24, 2024–(BUSINESS WIRE)–TSMC (TWSE: 2330, NYSE: TSM) today announced that its 2024 North American Technology will bring advanced semiconductor processes, advanced packaging and silicon leadership to power the next generation of AI innovation. , and 3D IC technology. Symposium. TSMC debuted TSMC A16TM The technology features cutting-edge nanosheet transistors with an innovative backside power rail solution for production in 2026, significantly increasing logic density and performance. TSMC also introduced System-on-Wafer (TSMC-SoW™) technology, an innovative solution that brings game-changing performance to the wafer level when addressing future AI requirements for hyperscalar data centers.
This year marks the 30th anniversaryth It's the anniversary of TSMC's North American Technology Symposium, an event that attracted more than 2,000 attendees, an increase from fewer than 100 attendees 30 years ago. His TSMC Technology Symposium will begin around the world in the coming months at the North American Technology Symposium in Santa Clara, California. The symposium will also feature an “Innovation Zone” designed to highlight the technology achievements of emerging startup customers.
TSMC CEO Dr. CC Wei said, “We are entering an AI-powered world where artificial intelligence runs not only in data centers, but also in PCs, mobile devices, cars, and even the Internet of Things. It will become.” “At TSMC, we offer the most comprehensive technology to realize your AI vision, from the world's most advanced silicon, to a broad portfolio of cutting-edge packaging and 3D IC platforms, to specialized technologies that integrate the digital and digital worlds. We provide our customers with a set of real world products.
New technologies introduced at the symposium include:
TSMC A16TM technology: TSMC's industry-leading N3E technology is now in volume production, N2 is on track for volume production in late 2025, and TSMC has debuted the next technology on its roadmap, A16. The A16 will combine TSMC's super power rail architecture with nanosheet transistors for planned production in 2026. Dedicating front-side routing resources to signals increases logic density and performance, making the A16 ideal for HPC products with complex signal routes and dense power delivery networks. Compared to TSMC's N2P process, A16 achieves 8-10% speedup at the same V.DD (positive supply voltage), 15-20% power reduction at the same speed, and up to 1.10x improvement in chip density for data center products.
TSMC NanoflexTM Nanosheet transistor innovation: TSMC's upcoming N2 technology will come with TSMC NanoFlex, the company's next breakthrough in co-optimization of design technology. TSMC NanoFlex provides designers with the flexibility of his N2 standard cell, a fundamental building block in chip design. Short cells emphasize small area and superior power efficiency, while tall cells maximize performance. Customers can optimize the combination of short and tall cells within the same design block and tune their designs to achieve the best power, performance, and area tradeoffs for their applications.
N4C technology: To bring TSMC's advanced technology to a wider range of applications, TSMC is introducing N4C, an enhanced version of its N4P technology that reduces die cost by up to 8.5% and reduces deployment effort, with volume production scheduled for 2025. N4C provides area-efficient foundation IP and designs. This rule is fully compatible with the widely adopted N4P, which enables yield improvements through die size reduction and helps value-tier products move into his TSMC's next advanced technology node. We offer cost-effective options.
Cois®SoIC, and System-on-Wafer (TSMC-SoW™): TSMC's Chip-on-Wafer-on-Substrate (CoWoS)®) has been a key enabler of the AI revolution by allowing customers to put more processor cores and high-bandwidth memory (HBM) stacks side-by-side in a single interposer. At the same time, our System on Integrated Chips (SoICs) have established themselves as the leading solution for 3D chip stacking, and for the ultimate system-in-package (SiP) integration, our CoWoS can be integrated into his SoICs and other An increasing number of customers are combining this with other components.
With System on Wafer, TSMC offers an innovative new option to pack a large number of die on a 300mm wafer, significantly reducing data center footprint while providing more compute power and lower per watt improve performance by orders of magnitude. TSMC's first SoW product, a logic-only wafer based on integrated fan-out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled for completion in 2027 and will integrate SoICs, HBMs, and other components to create powerful Create wafer-level systems. server.
Silicon photonics integration: TSMC is developing Compact Universal Photonic Engine (COUPE™) technology to support the explosive growth in data transmission associated with the AI boom. COUPE uses SoIC-X chip stacking technology to stack electrical die on top of photonic die, resulting in the lowest impedance at the die-to-die interface and higher energy efficiency than traditional stacking methods. TSMC plans to qualify COUPE as a small form-factor pluggable in 2025 and then integrate it into CoWoS packages as co-packaged optics (CPO) in 2026, bringing optical connectivity directly into the package.
Advanced packaging for automotive: After introducing the N3AE “Auto Early” process in 2023, TSMC will integrate advanced silicon and advanced packaging to deliver better computing to meet highway safety and quality demands. We will continue to meet the needs of automotive customers who demand performance. TSMC aims to achieve AEC-Q100 Grade 2 certification by the fourth quarter of 2025 with InFO-oS and CoWoS for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers. -R Developing solutions.
About TSMC
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has remained the world's leading purpose-built semiconductor foundry ever since. We support a thriving ecosystem of customers around the world and partner with our portfolio of industry-leading process technologies and design support solutions to bring innovation to the global semiconductor industry. With global operations spanning Asia, Europe and North America, TSMC is a committed corporate citizen around the world.
By providing a wide range of advanced, professional and advanced packaging technology services, TSMC implemented 288 different process technologies and manufactured 11,895 products for 528 customers in 2023. Our company is headquartered in Hsinchu, Taiwan. For more information, please visit https://www.tsmc.com.
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contact address
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Phone: 886-3-505-5901
Media contact:
Nina Cao
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Phone: 886-3-563-6688 extension 7125036
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michael kramer
public relations
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Email: pdkramer@tsmc.com
